Inhaltsverzeichnis
PPT-Folie
PPT-Folie
PPT-Folie
Latency from processor to various locations
PPT-Folie
PPT-Folie
PPT-Folie
16 processor SR8000
System Architecture SR 8000
PPT-Folie
SR-8000: Memory Hierarchy
Address Translation
Large TLB
Topology SR-8000
Parameter debis-SFR Hitachi SR-8000
PPT-Folie
CPU Architecture
Slide Window Registers
Instruction Set Extensions
Programming Models
SR8000 Parallel Programming Models
Pre-fetch and Pre-load
Software Pipelining
Pre-fetch
Pre-load
Pseudo-vector Processing
Effect of PVP
COMPAS
Hardware Support
Effect of COMPAS: Dot product: S = A(1:N)*B(1:N)
Remote DMA
Inter-node MPI
Intra-node MPI
SR8000: Parallelism on all levels
Key Features of SR8000
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